Method for allowing generate Makefiles to internally environment variables

I use cmake to compile projects with many subdirectories that can be built independently. Sometimes, during debugging, I’d like to recompile just one of those subdirectories with a different optimization level for debugging. There is an option to go back and change the CMakeLists.txt file for that subdirectory. However, it would be more convenient if I could just do something like OPT=-O0 make all -j 10.

In order for this to work, I would need to be able to do something like

add_compile_options($(OPT))

where compile options wouldn’t escape anything. This would lead to the OPT Makefile variable being used in the compile options, which would allow me to set it via an environment variable. However, the generated Makefile gets "\$(OPT)" rather than $(OPT). I’ve tried with string literals as well, but as mentioned in this post, certain characters still get escaped. Is this possible, or is the only option to go back and modify CMakeLists.txt?